1. Field of the Invention
The present invention relates to an image pickup apparatus for reducing 1/f noise generated in a transistor.
2. Related Background Art
FIG. 1 shows the circuit arrangement of a conventional MOS sensor cell contained in an image pickup apparatus. The MOS sensor cell is formed from a photodiode 201, amplifier MOS transistor 202, selector transistor 203, and reset transistor 204. Signal charges generated in the photodiode 201 in accordance with incident light are converted into a voltage by a parasitic capacitance in the gate terminal of the amplifier MOS transistor 202. A HIGH-level signal is applied to the gate terminal of the selector transistor 203, and then the selector transistor 203 is turned on. The gate signal voltage of the amplifier transistor 202 is output from the source terminal of the amplifier transistor 202 which has a source follower circuit arrangement.
When this sensor cell is not selected, a LOW voltage is supplied to the gate terminal of the selector transistor 203 to keep the selector transistor 203 off. The source voltage of the amplifier transistor 202 charges the parasitic capacitance in the source terminal to gradually increase the source voltage.
FIG. 2 shows an example of a conventional image pickup apparatus where a plurality of sensor cells described above are two-dimensionally arrayed. The image pickup apparatus comprises sensor cells 301, horizontal transfer switches 302, and a horizontal shift register 303 which sequentially turns on the horizontal transfer switches 302, a vertical shift register 304 which selects and activates a sensor cell, an output amplifier 305, an output terminal 306, and noise elimination circuits 310.
The sensor cell 301 has the same arrangement as that in FIG. 1. In many cases, the outputs of photoelectric conversion elements on each column are connected to a vertical signal line 308, and an impedance conversion MOS source follower 309 is inserted in the vertical signal line 308. In general, the source follower 309 is not turned on/off and continuously operates while the power supply is ON.
The output of the impedance conversion MOS source follower 309 is generally connected to the noise elimination circuit 310 for eliminating noises generated by manufacturing variations in the sensor cell 301 and MOS source follower circuit 309.
FIG. 3 shows the circuit arrangement of another conventional MOS photoelectric conversion element. The photoelectric conversion element comprises a photodiode 1, an amplifier MOS transistor 2, a selector transistor 3, a reset transistor 4, a constant current source 5 which supplies a bias current to the amplifier transistor 2, and a transfer switch 6 which transfers charges from the photodiode 1 to the input of the amplifier transistor 2. Signal charges generated in the photodiode 1 in accordance with incident light are converted into a voltage by a parasitic capacitance in the gate terminal of the amplifier MOS transistor 2. A HIGH-level signal is applied to the gate terminal of the selector transistor 3, and then the selector transistor 3 is turned on. The gate signal voltage of the amplifier transistor 2 is output from the source terminal of the amplifier transistor 2 which has a source follower circuit arrangement.
When this sensor cell is not selected, a LOW voltage is supplied to the gate terminal of the selector transistor 3 to keep the selector transistor 3 off. The source voltage of the amplifier transistor 2 charges the parasitic capacitance in the source terminal to gradually increase the source voltage.
FIG. 4 shows an example of a conventional photoelectric conversion apparatus where a plurality of sensor cells described above are two-dimensionally arrayed. The photoelectric conversion apparatus comprises sensor cells 100, sensor cell selection signal lines 101, sensor reset signal lines 102, sensor signal transfer signal lines 103, horizontal transfer switches 16, a horizontal transfer shift register 14 which sequentially turns on the horizontal transfer switches 16, a vertical shift register 15 which drives the signal lines 101, reset signal lines 102, and transfer signal lines 103 for selecting and activating sensor cells, an output amplifier 17, an output terminal 18, and noise elimination circuits 10.
The sensor cell 100 has the same arrangement as that in FIG. 3. The outputs of sensor cells on each column are connected to a vertical signal line 8, and the vertical signal line is generally connected to the noise elimination circuit 10 for eliminating noise generated by manufacturing variations in a sensor cell.
The operation of the conventional image pickup apparatus will be briefly described with reference to the timing chart of FIG. 5. Assume that the noise elimination circuit 10 obtains some differential output by using an output when the sensor is reset, and a signal output corresponding to an optical output.
Sensor cells on the first row are selected by a pulse 12201 applied to a signal line 101-1, the reset transistor 4 is turned on by a pulse 12202 applied to a reset signal line 102-1, and a corresponding output (Vres) is output to the vertical signal line 8. Subsequently, a transfer switch 6 is turned on by a pulse 12203 applied to a transfer signal line 103-1, and a signal (Vsig) corresponding to an optical signal input to the sensor is output to the vertical signal line 8. The noise elimination circuit 10 performs subtraction of the two signals Vres and Vsig to eliminate noise generated in the sensor cell. The noise-eliminated signal is sequentially activated by pulses 12204 to 12206 for driving the horizontal transfer switch 16. Sensor output signals on the first row are sequentially obtained by the output amplifier 17 via a horizontal signal line 19.
The gate widths and lengths of the amplifier transistor 2 and selector transistor 3 in FIG. 3 are set to very small in order to downsize the photoelectric conversion element. In particularly, needs for high-density image pickup elements have recently grown. The amplifier transistor which constitutes a sensor cell is often set to a minimum size enough to be achieved by the manufacturing process.
A noise power density Vn2 of 1/f noise in a MOS transistor is generally given byVn2=K/(W×L×Cox×f)where K: constant of proportionality                W: gate width of MOS transistor        L: gate length of MOS transistor        Cox: capacitance per unit area        f: frequency        
As is apparent from this equation, 1/f noise is inversely proportional to the product of the gate length L and gate width W of the MOS transistor. Hence, 1/f noise increases in the amplifier transistor 2 whose gate area is set small. As described above, an output from the amplifier transistor 2 passes through the noise elimination circuit which suppresses mainly noise of a DC component such as the threshold voltage of the amplifier transistor by performing sampling and subtraction for noise reduction. Upon sampling, aliasing of 1/f noise occurs at the sampling frequency and its harmonics, undesirably increasing noise in a wider band. In general, an output from the noise elimination circuit is amplified until the output is output from a final output terminal. Considering a transfer function viewed from the final output or the need for downsizing the amplifier transistor 2 in order to downsize the sensor cell, the noise contribution of the amplifier transistor 2 inevitably becomes larger than another MOS transistor serving as a 1/f noise source. When the MOS transistor is used as a switch, the drain-source voltage becomes almost 0 in an ON state, the drain current becomes almost 0 in an OFF state, and thus 1/f noise can be ignored.
As described above, it is important to reduce 1/f noise in the amplifier transistor 2 within the sensor cell 100 in order to reduce 1/f noise at a final output terminal.
As a method of reducing 1/f noise in a MOS transistor, “1/f noise reduction of metal-oxide-semiconductor transistors by cycling from inversion to accumulation” is described in Applied Physics Letters Apr. 15, 1991 p. 1664–p. 1667.
According to this method, 1/f noise itself is reduced by switching a MOS transistor between two, ON and OFF states. FIG. 6 shows a 1/f noise measurement example for a duty cycle of 50% (IEEE Journal of Solid-State Circuits, vol. 35, No 7, JULY 2000, “Reducing MOSFET 1/f Noise and Power Consumption by Switched Biasing”). The result “0 V” means that the gate voltage before the OFF state is 0 V. The 1/f noise spectrum is lower by 8 db than a modulation theory value.
This result is applied to a conventional image pickup apparatus. The OFF time of the amplifier transistor in the sensor cell changes an output from the photoelectric conversion element into an intermittent waveform, failing to obtain a normal output.
If a switch for changing the amplifier transistor to an accumulation state is arranged in each sensor cell, the sensor cell size becomes larger. The switch requires a driving line for driving the switch, further increasing the size. In gate reset operation of the amplifier transistor 2 in the circuit arrangement and operation of the conventional sensor cell as shown in FIG. 3, the source of the amplifier transistor 2 is connected to only a bias current source and capacitance. Thus, while the amplifier transistor 2 is selected, it maintains the ON state. If the gate terminal of the amplifier transistor 2 is reset while the amplifier transistor 2 remains unselected, the voltage of the source terminal changes following the gate terminal voltage and charges the parasitic capacitance in the source terminal. The source voltage gradually rises, and the amplifier transistor 2 gradually comes to a sub-threshold state. However, the amplifier transistor 2 does not reach the OFF state or accumulation state, and 1/f noise in the amplifier transistor 2 cannot be suppressed in the prior art.
As another prior art of performing reset operation, there is proposed reset of a vertical signal line as shown in FIG. 7 (e.g., Japanese Laid-Open Patent Application No. 2000-4399). In FIG. 7, a reset switch M8 resets a vertical signal line. Reset by the switch M8 is performed at a timing different from the timings of reset within sensor cells S11 to Smn. Since selector switches are not simultaneously turned on while reset operation within the sensor cell and reset of the vertical signal line are performed, the reset voltage of a vertical signal line V1 is not applied to the source terminals of the amplifier transistors 2 in the sensor cells S11 to Smn. At this time, even if the reset voltage is applied to the source terminal of the amplifier transistor 2, the gate terminal of the amplifier transistor 2 has only a small parasitic capacitance. A change in source voltage is, therefore, transferred to the gate voltage by the feedback effect of the parasitic capacitance between the gate and source of the amplifier transistor 2. As a result, the gate-source voltage hardly changes, and the amplifier transistor 2 does not shift to the OFF state or accumulation state.